Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
A point is unreachable typically means it is not going to any visible output, where it can be verified such as D of Latch/FF or O/p port, it is probably getting masked somewhere in the logic.
In ur case since it is causing problems at higher level of hierarchy, u could try and force it 0 or 1...
Nand2 is used as a general circuit for calculating Gate count, Possible reasons are
1) Nand is a universal gate
You can ask NOR is also a universal gate so why not nand gate, it is well known that although you can use both NAND or NOR to get any other logic , NAND is more commonly used because...
If you want to optimise the path, i feel its better to set a MAX delay between these two clocks, ofcourse to set a realistic max delay you will need the relation ship between the two clks as rjainv and Nir pointed out.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
