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Initial
wait_order (a,b,c);
Which from below initial process will cause that below wait order will pass.
a)
initial begin
#1;
q->a;
q->b;
q->c;
end
b)
initial begin
o#1;
->a;
end
always@a ->b;
always@b -> c;
c)
initial begin
#1;
->a;
#0 ->b;
->>c;
end
d)...
HI all ,
Thanks to all for your humble response, Can any body share me a piece of code regarding multiplier using shift and add method, I believe this would help me in a good way.
Thanks
arpit
Hi all,
Please provide me some valuable inputs regarding multiplier using shift and add method in verilog.
say : multiplicand and multiplier be two inputs of 8 and 6 bits respectively.
and it should follow 2's compliment of positive numbers
Note :- 2's compliment of a positive number is the...
HI dave_59,
sry for late response , was stuck in some other work.
Now , about my 2nd question 10 is an invalid state or a dont care condition.
How this will affect the synthesis part?
Kindly help me in that :)
Thanks
Arpit
HI Ajitrefs,
Basically you have cleared my doubt abt my 1st question , isnt it ?
can you briefly explain which one is more important code or functional , well according to me both are having their own importance . isnt it ?
And could u help e out abt 2nd question a little
Thanks
Arpit
Hi all ,
I Have two questions , both are related to coveage . Please help me .:-
1. If code coverage is 70% and functional coverage is 100% then
a) what conclusion we can drive from this statement ?
b) what do we infer from our design ?
c) How to correct this one ?
2. Suppose we are...
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