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Hello Klaus,
Thank you for your answer. What does data interrupt mean? I've been looking online, for example, design from Xilinx, and also read the documentation. I still don't have a clear understanding of what it really means though.
I am working with the uartns driver, but am having some difficulties understanding the following function:
/****************************************************************************/
/**
*
* Sets the options for the specified driver instance. The options are
* implemented as bit masks such...
The issue is not connecting the IPs to one another. The issue is how the different IPs are supposed to be connected when the example software design is taken into account.
Consider the following scenario: I want to run these sample applications. Given that these examples are aimed at the UART-lite, I know that the Vivado block design will include the AXI Uartlite IP. Also, because I am working with multiple applications, it is natural for me to assume that the...
Hello,
When creating a run configuration for one of my application projects at Target Setup I am given a choice to "Use FSBL flow for initialization" (see attached image). What is meant by this?
The summary also becomes different (see image).
I ran the application without choosing "Use FSBL...
Hi,
Is this to say that in order to get the TCL script, I'll have to copy and paste each update from the TCL console into a notepad? Is there no way for Vivado to save TCL commands automatically?
Best regards,
Armin
Hello,
I'm interested in learning how to write my own .tcl script in Vivado for a certain hardware design.
Many examples I've seen online simply provide a .tcl script that allows the user to "source" this file and have everything done for them.
Your point is well taken. The program does, in fact, need the use of four different IP addresses:
* CPU
* UART
* CLOCKS
* INTERCONNECT
* RESET
What I'm not sure about is how they're meant to be linked together. To ensure that the software code and the hardware design are in sync.
Regards,
Armin
When wanting to experiment with different IPs as an example the AXI UART16550 how is one supposed to design the block design in order to make the Xilinx C examples "correspond" well with the exported block design.
As an example. When wanting to experiment with this C code...
So, I've revised my block design to look like this: (see PDF attachment).
External ports are linked in this manner (see image attachment).
The Vivado hardware design has been exported to Vitis, and I'm currently working on an application project that implements interrupt on both the receiving...
Hello,
I agree with the direct connection from AXI UART interrupt to CPU interrupt. I just do this in case I want to connect the interrupt signal to my oscilloscope, just to visualize the signal (practice reasons). I am feeling quite relaxed with the Block design side of my project. It's as...
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