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Recent content by Armand86

  1. A

    problem with VHDL mealy sequence detector

    thanks for support, problem solved :)
  2. A

    problem with VHDL mealy sequence detector

    i am not very skilled with VHDL code, can you show me how to modify mine? solution with testbench seems not to work well. Thanks
  3. A

    problem with VHDL mealy sequence detector

    i have made the same machine with Moore and it works perfectly, why?
  4. A

    problem with VHDL mealy sequence detector

    hello, i need help with VHDL sequence detector (101) project. I wrote VHDL file but output dout goes to 1 when machine is on "Next state" and not on "Present state". In other words machine gives output 1 on the falling edge of clock and not rising edge. anyone can help me? thanks library IEEE...
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