Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by arjun2145

  1. A

    How shared access mode and Crossbar mode works in AXI

    Hi, How Crossbar mode and Shared access mode in AXI Interconnect worksIN DETATIL? In Crossbar mode if multiple masters tryin to access same slave, which master gets the priority? Does the other master has to wait till the completion of First master?. In Shared access mode, why read got the...
  2. A

    Why Bus protocols should support 1024 bits, when processor are working with 64bits?

    If the processors are working with 64bits, then why do they need Bus protocols to be as high as 1024bits. Is it for re usability?
  3. A

    write response in AXI

    Hi Sunray, As AXI supports outstanding transactions, for a write transaction the response would come for the entire burst not for each beat. so, WLAST indicates the last beat of the transaction. WLAST/RLAST does not give any response information of a transaction. For a read transaction, the...
  4. A

    Interleaving and Out of order

    Hi Vasanth, Data Interleaving: In a multi master interconnect, lets consider master A initiated the transfer with a burst of 4 and master B with a burst of 2 then it follows as A1 B1 A2 B2 A3 A4 it means A started the transaction, then went to B because of idle cycle by A and again A likewise...
  5. A

    Write data interleaving - AXI

    Re: axi interleaving Hi amaresh, when multiple masters are connected, suppose master1 and master2 wants to perform a write transaction to the same slave then Master1 with burst of 4 and Master2 with a burst 8 Master1 Master1 Master2 Master2 Master2 .. . Master1 Master1 which means that as...
  6. A

    Why worst case delay reports Setup violations and best case reports Hold violations.

    Hi All, i've a confusion why worst case report is considered as the Max delay violation(Setup violation) and Best case report as Min delay(hold violations). And why we always calculate the hold violations at the launching flop. thanks in advance, Arjun

Part and Inventory Search

Back
Top