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I have ram design in that design one sub module as inout port.
I have used continuous assignment statement to assign input and output to that inout port
assign d1=(WR1 && !RD1 && (!SF && !AF))?din:0;
assign d2=(WR2 &&!RD2 &&(!SF && !AF))?din:0;
assign d3=(WR3 &&!RD3 &&(!SF &&...
Error-[SFCOR] Source file cannot be opened
Source file "fsm_trans.sv" cannot be opened for reading due to 'Not a
directory'.
Please fix above issue and compile again.
"../lib/fsm_env.sv", 3
Source info: `include "fsm_trans.sv"
I got the error while compiling with the command
vcs...
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