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hey there,
i am trying to simulate the mod operation in modelsim and i am not getting a proper output.
my code is
entity divi is
port( a,b : in std_logic_vector(15 downto 0);
y : out std_logic_vector(15 downto 0)
);
end divi;
architecture ber of divi is
signal a1,b1,c1 ...
hey there,
i am trying to simulate the mod operation in modelsim and i am not getting a proper output.
my code is
entity divi is
port( a,b : in std_logic_vector(15 downto 0);
y : out std_logic_vector(15 downto 0)
);
end divi...
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