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ratio of pmos nmos width =2
The reason you would find a beta ratio equal to 1 in some instances is because, when the transmission gate is turned-on, both the pmos and nmos are turned on and are in parallel. Even though only the pfet is good at passing '1' and nfet is good at passing '0', they...
Following is an explanation of the circuit behavior. I hope it is not too confusing.
first some naming:
pu_l : left pull-up pfet
pu_r: right pull-up pfet
pd_l: left pull-down nfet
pd_r: right pull-down nfet
int_l: drain of pd_l and drain of pu_l
int_r: drain of pd_r and pu_r
initial...
It looks like you are ramping up the VDD power supply in the begining. My guess is that, the internal nodes of the 1000 inverter chain far away from the input signal will end up initializing to the wrong level with respect to the initial input level. you can test this by monitoring the internal...
The reverse biased diode is probably an antenna diode. It shouldn't be an issue in my opinion.
If the clock waveform is completely out of whack, I would suspect some thing more basic like some input pins floating etc. Hsim automatically assumes that inputs that are not driven by an input...
Re: skew
Hi MarcS, I agree with you reg local skew and global skew. But one question is, does STA include clock skew when it measures hold and setup margins? My experience as a custom circuit designer is that STA assumes that all clocks are ideal with no skew when it measures setup and hold...
Re: skew
Skew is ABSOLUTELY critical. Lets say you have a hold margin of 50ps in a flop-flop path and the skew is >50ps, then your circuit will definitely fail at any frequency.
Added after 2 minutes:
in my above example, I am assuming that the hold margin is measured assuming an ideal...
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assign int=input|output
always @(posedge clk)
output<=int
---------------------
syntax is not accurate... but logic should be correct.
assuming that output is initialized to '0'
Added after 6 minutes:
sorry... earlier solution is wrong... the following should work...
Re: About delay in MOS
That is not the conclusion to be drawn from my description of delay.
Below is an equation for the delay of a gate based on logical effort methodology.
Delay = a*(Cself/Cin) + b*(Cload/Cin)
= K + LE*fo
Cin= input capacitance of the driving gate
Cself =...
asynchronous clock domain
Thats a good example.
Metastable means exactly what it says, "meta"-"stable".
If you were to look at the butterfly curve for the feedback path of a latch, it has two stable points (vdd,0) and (0,vdd) and one metastable point close to (vdd/2, vdd/2) depending on how...
clock domain crossing techniques
Hi Asic_intl,
If we consider only the MSB in my example, there is no logic problem, only latency problem. If we were monitoring only the MSB in the sampling domain, we will observe the transition from '0' to '1' one cycle late in the event of metastability...
Total energy dissipated per charge+discharge cycle of a cap Cload is Cload*Vdd^2.
In the charge cycle, the PMOS dissipates 1/2*Cload*Vdd^2 energy and another 1/2*Cload*Vdd^2 energy is transferred to the cap Cload that stores it.
In the following discharge cycle, the NMOS dissipates the...
You can assert the reset pin of the flops that you are using to implement the phase detector to start in a known state.
For simulation in spice, you can also use the ".ic" statement to initialize the internal latch node of the flops to the desired state.
In short, that is true. But you will not know whether it will end up as logic '1' or '0'.
Electrically, even if it initially starts up in an intermediate voltage level (i.e, in metastable state), there will be enough noise and parameter variation in the latch feedback to push it towards either...
Re: About delay in MOS
Delay in a gate can be simplified as the amount of time it takes to discharge the load capacitance that the gate or fet is driving.
I= q/t = C*V/t
t=C*V/I
1) to the first order, delay (time) is inversely proportional to drive current. So, increasing the drive current...
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