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Recent content by Anuvesh

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    propagation delay with voltage swing

    voltage swing means signal transition from low to high.propagation delay depends on transition time. - - - Updated - - - voltage swing means signal transition from low to high.propagation delay depends on transition time.
  2. A

    Synthesis clock frequency

    is it tool dependent..??
  3. A

    Synthesis clock frequency

    maximum operating frequency means how much..???
  4. A

    Synthesis clock frequency

    sorry,, if i don't have any clock constraint in my SDC then what happens??? what frequency it ll consider at the time of synthesis STA..??
  5. A

    Synthesis clock frequency

    hi friends, At the time of synthesis, if i am given any clock constraint in SDC then it is synthesisable or not ?? if synthesis is done which clock frequency it ll consider ?? please can any one clear my doubt.
  6. A

    Filler cells or metal filling...????

    hi friends, i have one doubt. we are using filler cells in between physical design flow right, and metal filling is used at the final stage. what is the difference in between these two?? can any one explain on this
  7. A

    TCL scripting exixution

    i already installed that active tcl.......after installing active TCl how will i exicute a tcl script
  8. A

    TCL scripting exixution

    hai friends, can any one help me out how to exicute TCL scripting in windows operating system.
  9. A

    C MOS Fundamentals question

    what is N well continuity in cmos circuits ??????
  10. A

    time borrowing in static timing analss...

    can u please shere that primetime manual
  11. A

    Hold, setup check for multi cycle path

    if provide multicycle path 3 then we check setup time at 4th edge and we check the hold check at the 1st edge of the capture clock signal.
  12. A

    vlsi physical design:::

    In my view if utilization is increased the cell count ll increase,so the connectivity resources must increases so the metal layers are increased.

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