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hi sorry for missing the correct schematic,
what i mean is the red circle above. For conventional one, there is no such additional logic gates
Could you explain a little more detail?
hi everybody,
I need a help.
this is circuit for 4-stagge johnson counter circuit. i wonder why they add 2 gates AND & NOR while it could be designed this conventional counter with only feedback and decoder circuit (8 AND gates).
thanks,
Hi ads_ee, this is a kind of mix-signal design - clock dividers associating with an RF design in my circuit. So it is hard to post it in an individual RF section with only pure RF expert's help. Please sympathize with the situation.
P/S: i 've just looked at the section name, it is digital...
thanks for your hint above, the circuit seems to be functioned but the "shape" is not that good because of high frequency operation and there are some unexpected shooting right after LO1 LO3 & LO7 in 1 period. Is there any ways to improve this issue, could y give me a suggestion ? honestly im...
sorry for missing your above comment,
generally, i hope it should be like this (sorry for my bad sketching skill)
fortunately, i find here an idea at last post(https://www.edaboard.com/threads/4-phases-non-overlapping-clock-generator.342504/) - of providing 4-non overlapping phases with only...
Actually, based on the idea in the link of my post, i already built a clock divider with 4 phases non-overlapping but, input clock of 4GHz and output clock 1 GHz. Of course, as your comments, i traded off such a large spikes at the falling egde like the capture below. However, it is still fine...
Hi EDA members,
I want to design a 8 phases non-overlapping circuit from johnson divider by 4 circuit. I already referred to this post for a hint:
https://www.edaboard.com/threads/4-phases-non-overlapping-clock-generator.342504/
But the thing is my clock input has constraints that I cannot make...
you can but your signal at output finally s always small hence it never reaches the requirement of the subsequent stages
If you wanna make it larger you have to make sure that your second stage has such an extremely huge P1dB point in order to keep the output signal not saturated
[p1db(total)...
Yeah, all terminals are shorted together for Mosfet capacitors, that is weird to what i have seen so far. Can i remove the R0 here ?
- - - Updated - - -
For 1) because I connect the power supply directly to this PAD to bias for LNA, so can i remove this resistor ? because in term of noise, NF...
Hi all circuit designers,
I have 2 questions reagarding biasing a LNA, as shown in the capture below:
1/ For what i ve known so far, the R0 resistor is employed as a large enough value to restrict the noise current contribution from current mirror into core LNA devices. However, if I have...
you are possible using a quadrature hybrid coupler (a type of directional coupler) as a combiner at the cost of 3 dB attenuation at branches 2 and 3/ output at 1 port and isolation matched load at port 4 ( please refer to Pozar book: microwave engineering for more detail).
this technique is quite popularly used in bandpass modulation in Digital communication, you need to take a look at "Digital Communication book" (maybe chapter 4) from Prof. SKLAR first, then go further to mod/demo circuit later
I think you had better show your input impedance to examine whether or not your process is possible of doing input matching.
Because any BJT has a rpi in parallel with Ccb hence we are possibly able to do matching with L-C fundamental structure. If inductors or capacitors are enormous...
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