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Buffer relocation, Gate sizing, Buffer insertion ( delay insertion), buffer sizing, gate relocation are some of the common CTS optimization techniques.
pnet_options( power net placement blockages) sets up placement tools to avoid power strap violations which in turn leads to congestion and IR drop issues.
Partial pnet allows standard cells to be placed under pnets,but the pins in the standard cells are checked to prevent shorts with the pnets...
Non- Default routing rules like double spacing, double width, shielding etc are used to make the clock routes less sensitive to cross talk or EM effects.
Hence to avoid such effects at the later stage we should give the NDrules atthe CTS stage itself.
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