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Recent content by ankit rajput

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    Error during hardware software co-simulation using ZCU102 board

    Hi I am trying to do hardware software co-simulation using ZCU 102 zynq ultrascale board. I am able to generate hardware software co-sim block as shown below: **broken link removed** but when I add add this block to simulink and try to run i get the following error: **broken link removed**...
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    how to generate 4MHz clock from 2 MHz clock.

    i am using the same xapp868 design for clock recovery. I was saying that in the verilog code of this xapp868, phase width of 16 has been taken instead of 32.
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    how to generate 4MHz clock from 2 MHz clock.

    I tried to do that. The VCO file(voltage controlled oscillator) is in .ngc format. So , I cannot open it. But even i tried to take phase [14] (because in verilog example phase width is 16 instead of 32) . But phase [14] or phase [15] is not at all related to 2 MHz or 4 MHz clock output. what is...
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    [SOLVED] Values of set/ reset when Instantiating ODDR?

    thanks for quick reply. I have already seen this document. But I don't understand that suppose "SRTYPE" is ASYNC then what should be the values of set and reset?
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    [SOLVED] Values of set/ reset when Instantiating ODDR?

    hi, when we instantiate ODDR then how to provide value to "SRTYPE" and set/reset. I mean for "async" and "sync" in SRTYPE what should be the value in set /reset?
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    how to generate 4MHz clock from 2 MHz clock.

    oh.. I didn't knew that. Let me check how to generate 4 MHz along with 2 MHz clock.
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    how to generate 4MHz clock from 2 MHz clock.

    My input is a 2 MHz data coming from another Arty FPGA board. and 2 MHz clock is recovered using the code mentioned in xilinx application note XAPP868 (https://www.xilinx.com/support/documentation/application_notes/xapp868.pdf).
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    how to generate 4MHz clock from 2 MHz clock.

    Arty board FPGA part : XC7A35TICSG324-1L
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    how to generate 4MHz clock from 2 MHz clock.

    The 2 Mhz clock is generated from the input data using the clock recovery algorithm. I require one 4 MHZ clock that must be synchronize to this 2 MHz clock. If i use arty board clock to generate 4 MHz than both clock would not be synchronize. and i don't know how to synchronize/align two clocks...
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    how to generate 4MHz clock from 2 MHz clock.

    Hi, I need to generate 4 Mhz clock from 2 MHz clock . I checked clocking wizard/MMCM/PLL , but there input clock range start from 10 MHz. I had read about using rising and falling edge detectors but they fail to give 50% duty cycle. can DDS(direct digital synthesizer ) convert 2MHz clock...
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    Receiving incorrect output at receiver FPGA

    thanks for reply. since i have never implemented any clock synchronization , is there any source about implementing it in FPGA?
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    Receiving incorrect output at receiver FPGA

    Hi, I am implementing QPSK transmitter and receiver on two different FPGA (Arty boards) and connecting them through PMod (I/O) pins. I have not implemented any clock recovery at receiver FPGA. So, sometime output is coming correct and sometime gliches are coming in output. let me explain further...
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