Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
Please help me to know the concept for merging intra domain clocks and inter domain clocks. what all things need to be taken into consideration?
Thanks in Advance,
Anju.
Hi,
Can you please tell me why we are using only D-type flip flops in scan insertion? what is the draw backs if we use any other flip flop?
Thanks and Regards,
Anju.
How do you detect a sequence of "1010" arriving serially from a signal line?
How do you detect a sequence of "1010" arriving serially from a signal line?
please help me to solve the problem. thank you.
While analysing the verification message TSV-385 in ET tool, I realised that the data pin in the scan chain is coming from tie_off cell and not from primary scan_in pin of top level design. So I need to disconnect the data_pin from tie_off cell. Please help me to do it. Is there any possible way...
Thank you for your reply. I am new to this tool and was converting one synopsis script to RTL compiler form in order to use it in ET tool. Thanks a lot.
Hi,
Please help me solve the problem regarding building a test mode in cadence encounter test tool. I am using the tool for generating ATPG patterns. While building a test mode, a sequence definition file in TBDPatt is needed. How can i generate the pattern. Please help me.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.