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Recent content by anhtuan

  1. anhtuan

    Information about the IP core certificate

    Re: IP certificate Don't have anyone can help me?
  2. anhtuan

    Information about the IP core certificate

    Re: IP certificate When you get a certificate of a prestige company or organization, it means your IP core has attained some standard by them so the customers don't have to worried about your IP quality! Thanks Peter Chang but i'm finding a organization who will check and certificate our IP ...
  3. anhtuan

    Information about the IP core certificate

    Hi everyone, Does anyone know about IP(intellectual property) core certificate ? Have any organization or company else certificate your IP core beside Altera ( AMMP approved) , Synopsys (openmore)?? thanks for your help !
  4. anhtuan

    Can we automatically translate schematic(or Verilog file ) to layout in Cadence?

    Re: Cadence Question!!! What tool of Cadence for translate from gate netlist to layout??
  5. anhtuan

    Can we automatically translate schematic(or Verilog file ) to layout in Cadence?

    Hi everyone! I have some question about Virtuoso Cadence Software . First, can we tranlate automatic from Schematic to Layout??? Second, can we translate automatic from Verilog file to Layout (like in Digital design by Synopsys Sofware)?? If yes , what steps to do in...
  6. anhtuan

    Which pin of EEPROM should be connected to pumping clock of charge pump?

    Re: charge pump So, the charge pump circuit must have self-osillator circuit??
  7. anhtuan

    Which pin of EEPROM should be connected to pumping clock of charge pump?

    Re: charge pump In EEPROM people use charge pump to provide voltage larger than voltage supply! so i think almost EPROM, EEPROM use charge pump! but in datasheet i can't find the pin for pump clock!!
  8. anhtuan

    Which pin of EEPROM should be connected to pumping clock of charge pump?

    Hi everybody! In EEPROM we usually use a charge pump circuit,and in charge pump circuit we have a pumping clock to control! But, i don't know what pin of EEPROM connect to this clock!!! Can anyone explain to me! thanks alot!
  9. anhtuan

    How to simulate an EEPROM?

    hi everyone! if we design an EEPROM (include design EEPROM cell), so how can we simulate it??what tech file for simulate and for DRC&LVS??thanks alot!
  10. anhtuan

    CMOS IC LAYOUT(Dan Clein)

    what software free so we can practise it??
  11. anhtuan

    Schematic Design Tool

    You can use Pspice , winspice (it's free, cheap) or comercial software like Cadence , Mentor , Tanner..!
  12. anhtuan

    VLSI-Design of Non-Volatile Memorie

    Re: Nonvolatile memory i searched all topic in this forum but can't find any useful document about EEPROM! Does anyone have materials in practical?? or give some advise for design EEPROM??
  13. anhtuan

    Looking for documents about EEPROM design flow

    I read some books but it's just instroduce about theories. So, does anyone have books or document detail about EPROM, EEPROM design flow in practicality??Thanks alots!
  14. anhtuan

    VLSI-Design of Non-Volatile Memorie

    Re: Nonvolatile memory Does this topic die??:| . Anyone have books or document about ROM, EPROM..??thank a lot!
  15. anhtuan

    How to solve SDF error: cannot find timing check?

    sdf error Yeah, my SDF file is 2.1 version. But what can i do to solve the problem? Should i: -Ignore the error (if this error is not important) -Or find a different version of library cell (if this error is important) Could you suggest me a solution? Thank you very much!
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