Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi i'm designing differential pair with active load.
Yellow curve is pulse input of differential amplifier.
Blue curve is output at drain of M49.
As you can see in the blue curve, rising edge is very fast but falling edge is quiet weird.
at first voltage falls slowly and then falls...
I've been studying inductorless LNAs.
and in almost every paper, LNA utilizes resistor as a load.
active load(current source load) is better because resistor load limits output voltage swing and active load's output impedance is higher.
why load of LNA is always resistor? not active load.
I...
Suppose OP-Amp is ideal and equivalent circuit of OP-amp is (a).
in case differential input is zero, output DC+AC level is zero. (a)
but real OP-Amp looks like (c), (d) and their output DC level is not zero.
1. in circuit (c) DC level of Vout is A = V(Iss)+Vov2+Vov4
2. in circuit (b) i think...
Suppose OP-Amp is ideal and equivalent circuit of OP-amp is (a).
in case differential input is zero, output DC+AC level is zero. (a)
but real OP-Amp looks like (c), (d) and their output DC level is not zero.
1. in circuit (c) DC level of Vout is A = V(Iss)+Vov2+Vov4
2. in circuit (b) i think...
I'm designing a CMOS inverter circuit.
Right side graph is output voltage.
My question is why is there a peaking at 1us, 2us, ...(yellow mark)
and how can i remove it?
i saw that sort of topology(switch between two current mirror). but i think you're right Vg3 is just floating, not dropped to 0V.
How can i fix this circuit to make Vgs3 changes alternatively 0 to 590mV by a pulse control signal to sourcing a pulsed on and off current to a resistor(R0)?
A. Situation
--------------------------------------------------------------------------
1. I wanna a pulsed current(1mA, 0mA) to a load resistor(R0).
2. M1, M3 are current mirror pairs.
3. M1 is generating a Vgs1(for 1mA) and M3 is copying a Vgs1 so that M3 can flow current of 1mA.
4. M2 is...
in Figure 7.39 (Razavi's Design of analog Cmos integrated circuits).
when calculating input-referred noise current(input is open), book said that produced output noise components is only In2(M2 noise).
and i don't understand why there is no noise components of Rd and In1(M1 noise).
i appreciate...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
