Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by anandhavel

  1. A

    [SOLVED] Finding path from Primary Inputs to a net in Design Compiler or PrimeTime

    Thanks for the help englishdogg. I found that "report_transitive_fanin" works.
  2. A

    [SOLVED] Finding path from Primary Inputs to a net in Design Compiler or PrimeTime

    Hi, If I specify a net in a verilog module, is it possible to find the primary inputs and path to the specified nets in either PrimeTime or DesignCompiler? Thanks, Anand
See more

Part and Inventory Search

Back
Top