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the following modules is required 255 ram locations of 8 bit wide.i am writing code like this.
module xy(x,y,ram);
input x,y;
output [7:0] ram[0:255];
reg[7:0] ram[0:255];
to assigning value of ram location i am writing like
ram[0]=data;
ram[1]=data;
ram[2]=data;
ram[3]=data...
we need in our program 256 loctions of 8 bit wide i.e., producing 256 Byte ram.
we are using it by array but we are geting error message for declaring the array. actually we are displaying the data stored in ram,therefore it is one output port, so in our program we are written code as follows...
can anybody answer for hardware speed Vs software speed. which one is faster?
for eg designing a router in FPGA vs software router... which one is best..?
Re: how to give the 16 bit input on fpga kit on spartan 3E??
if you use xilinx then in source window keep implementation /synthesis then in process window design utilities click the + mark. and give assign package pins.if you have spartan 3e kit manual there will be pin no for switches. enter...
verilog error check
my code need to check one bit in one clock.next bit in another clock. but it checking ann bits in one pos edge clk. please say correct way
module HighSpeedRouting(clk,res);
input clk;
output[15:0] res;
reg[15:0] res=16'b0...
Re: State machine
there are two state machines.
1.melay state machine(melay FSM)
2. moore state machine(moore FSM)
verilog code for this is thereb in digital design(3rd edition) by morris mano book.you can refer it.
Re: m.tech project
High Speed Routing.it important for recent environment. there are so many alogorithms for that . but programming and implementation is really tough.
i need verilog code for 4 bit btree .for eg. each node having some 5bit value. externally we are giving 4 bit value,that is 4 bit address. we are checking the adderess with btree by bit by bit. finally if address matches we are returning the value in that address.
please help me...
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