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Recent content by analogLow

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    Spectre command line vth output for each monte carlo run?

    Hi, I have successfully run a monte carlo (transient) and extracted the vth for each run (using the "finalOptime") option. Anyone know how to set this up same vth extraction in spectre command line? Adding the finalOptime option in the command line run only outputs a single monte carlo run...
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    transient simulation with random values

    Thanks to both of you for your ideas ... I finally got a chance to try them. The oscillator idea gave me another idea ... running the oscillator with monte-carlo. This gives enough variation/randomness to help me ... the only problem is the speed. The vprbs - source is what I ended up using to...
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    [SOLVED] [HELP] Low power VLSI design using Variable Body Biasing (VBB)Techniques

    Hello, VBB can very useful for tuning transistors in low power applications. With VBB, you are effectively you are tuning the threshold voltage of the transistor by applying voltage to the bulk. If you want low leakage (e.g. at low frequencies or in devices where leakage is a problem) then you...
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    transient simulation with random values

    Hi all, I have a data signal D that should change value at random times throughput X CLK cycles. For example, during the first cycle, D would change value e.g. at 30% of the CLK period and e.g. 54% during the next CLK period, etc. Each CLK period would see D changing at random times throughout...
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    [SOLVED] TSMC missing schematics ...

    Hi ... thanks for the reply. Is this tool activated from the CIW window? On the CIW window, there are PDK tools, but nothing for schematic import. Thanks, analogLow
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    [SOLVED] TSMC missing schematics ...

    Hello, I am trying a new TSMC design kit. The digital libraries are missing the schematic view. The layout view is there. For example, there is an inverter with a layout, but no schematic view. I have tried to use the CIW tools (e.g. generate schematic from netlist), but they all result in...
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    Wn/Wp in digital circuit

    Hi, > I mean that for wn/wp, 60/120 is same as 180/360? Yes and no. :) First, the ratio is important to ensure that the drive strength of the NMOS and PMOS are similar. You want the inverter to equal low-to-high and high-to-low transitions. So yes, in terms of matching the low-to-high and...
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    Channel formation in FD SOI

    Hi, >but manifested awful kink behaviors when you got above Vgs=0. Wow yeah that would be awful. So far I have not seen any kink effects due to the floating body (after a lot of sweeps and measurements). The IV curves are pretty ok even up to the nominal voltage. I have built a number of...
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    Channel formation in FD SOI

    Hi, Interesting discussion and good points. I can maybe add some input also. (Ultra-thin body and box) FD-SOI is what I have had experience with. The channel below the gate works just as a (bulk) MOSFET. For example, in an NMOS FD-SOI, if you apply a large enough Vg (e.g. Vg>*Vth), then the...
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    simulator options for low power

    hi, I am simulating a low power circuit (nanoWatt power consumption). Anyone have any recommendations on spice integration methods for this low power range? So far, it seems that the Backward-Euler method produces the most stable and realistic results. Thanks, analogLow :razz:
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    how can i calculate power dissipation in 9-stage ring oscillator

    Start here: https://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-78.html See page 148 for estimating power dissipation. For measuring with HSPICE, you just need to measure the VDD that supplies the ring oscillator: .meausure v(VDD)*i(VDD)
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    decreasing bottom plate parasitics in MOM capacitors

    thanks for all the tips ... in the end, I used higher metals and min. spacing and lots of vias. know i have much less bottom plate cap -analogLow
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    decreasing bottom plate parasitics in MOM capacitors

    Thanks >(. I am not clear what you mean by oxide cut. I mean the caps I am using are using are just metal / vertical parallel plates with no transistors underneath. analogLow
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    decreasing bottom plate parasitics in MOM capacitors

    Hi, I have modeled my mom cap and I need to reduce the bottom plate capacitance (Cbottom) further. Is it possible to reduce the Cbottom by placing an NWELL or DEEP NWELL (or something) under the cap? thanks, analogLow:-D
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    ocean corner simualtion

    That should pull up the window that allows you to select the process corner (e.g. TT,FF,SS,FS, or SF). Also, you can choose local variations there. Make sure to type "UartCornerSetup" into your Command Interpreter Window in Virtuoso. What process are you using?
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