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Recent content by analogdesignlove

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    infineon interview for analog mixed signal design intern

    Hi, I have an interview at Infineon technologies for the position of Analog mixed-signal design intern. Can someone please give me an idea about the interview experience and what I should expect? I am currently doing my master's in ECE.
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    Interfacing a co-processor to an axi bus

    Interfacing coprocessor to axi bus I have a crypto coprocessor which I am trying to interface to a platform through axi bus. The platform uses axi4 interconnect. I am having doubt that how to connect axi slave interface to the coprocessor. Also, there are already spi slave connected to axi4...
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    [moved] C code issue with giving data input

    Hi, I have a seizure detection algorithm in which data was stored in memory and then taken input from memory. I want to remove this stepand give data directly. I am not getting how to do that since the algorithm was not written by me. Can you help me with how to hard code the data?
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    Synopsys Primetime error in event file using vcd file from modelsim

    Actually I am not using .spef file to annotate parisitics and .sdf file is not read by new versions in primetime. Can I do power simulation without .spef file for parasitics in primetime?
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    Synopsys Primetime error in event file using vcd file from modelsim

    Hi, I want to run power analysis in synopsys primetime, and I have generated the netlist and the sdc file of my design as well as the vcd file from modelsim. But when I run the PrimeTime, there’s such error: Error: Can not find any event in the event file. (PWR-248) In the generated power...
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    Current design in prime time

    Can I do power simulation without .spef file for parasitics in primetime?
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    Current design in prime time

    I was using the following commands for generating the vcd file- vcd file correctmal.vcd vcd add -r /tb/* run 10ms Can you tell me if its correct?
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    Current design in prime time

    Hey, I generated the netlist successfully. Thanks for your inputs. Now, I am using the netlist file in primetime. I generated the vcd file for my application in modelsim. but in prime it shows error like below: Error: No activity is available in the VCD file for the given time interval for...
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    Current design in prime time

    Hey, I am getting the following error while elaborating the design Error: Width mismatch on port 'addr_i' of reference to 'sp_ram_bank' in 'sp_ram_wrap_RAM_SIZE32768_DATA_WIDTH32'. (LINK-3) Error: Unable to match ports of cell core_region_i/data_mem/sp_ram_bank_i ('sp_ram_bank') to...
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    Current design in prime time

    No, the netlist is a .v file. Actually I am synthesizing the netlist file for pulpino platform. But there are width mismatch. Can you tell me how to instantiate single ported memory macro based on a particular technology library?
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    Current design in prime time

    Hi, I am new to primetime. I got the netlist file and gave the search path for the design. But my design is a .sv file. How can I use that in primetime.
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    Problem while using primetime

    Hi, I am using pulpino platform and I want to do power analysis using synopsys prime time. Can someone help me with how to set the environment for primetime and how can I get netlist file for pulpino platform developed by ETH Zurich.
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