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Recent content by amsverif

  1. A

    Verilog task similar to $signal_force

    Thanks Dave for your reply. I want my environment to be portable and hence don't want $signal_force which is tool dependant. Its $signal_force for Modelsim and nc_force for NCSim. I have gone through some literature that the implementation I want to do is indeed possible but verilog can't do it...
  2. A

    Verilog task similar to $signal_force

    Hi All, I am creating a task in verilog that works similar to $signal_force verilog system task. But with a lesser number of arguments i.e. - Signal to force, value to be forced and the time at which the value is to be forced. As its not working for me I am working with 2 arguments -...
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