Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
this is actually my problem
i dont know how to calculate the noise , i have read in the literature that noise analysis in spectre isnt suitable for noise calculation in dynamic comparators and that one way is to calculate the noise from transient noise analysis but i dont know how this could be...
Iam trying to calculate the input referred noise of a strongarm dynamic comparator using cadence spectre simulator
the problem is that it calculates the spectral density of the noise and i want to calculate it as an rms voltage value
the netlist
the spectrum function settings are
no. of samples = 1048576
no. of noise bins = 0
start frequency = 0
end frequency = ـــــ default value
window type = blackman
ADC span = 0
measure type = snhr
ADC code
DAC code
no BigBoss
the ADC is also ideal with veriloga it should give me the ideal answer
and it did for the first 8-bits , but in the 9th bit through the 12th bit it gives me the same answer 49.4dB
i am using cadence IC 6.13 virtuoso to design an ADC
i am trying to measure the SNR of that ADC , so i build an ideal DAC using Veriloga and take the output of the ADC to the input of the DAC and then i took the output signal from the DAC and export it to the calculator of the Cadence and then...
can you please tell me how to find the parasitic capacitance in cadence IC 6.1.3
- - - Updated - - -
i have connected a circuit in cadence and i want to know the value of the parasitic capacitance at this node
my question is wither there is an analysis that could give me the value of the...
i am using the tsmc13rf pdk in cadence virtuoso
there is a lot of nmos types that i dont know what is the difference between them
nmos1v
nmos2v
nmos3v
nmos1vcap
nmos1vhvt
nmos1vlvt
nmos1vn
would anyone help me to identify the difference between this instances?
thanks KlausST but i want to calculate it from the data collected from the FFT i will attach the signal
it is a sine wave output for 4 bit Ideal ADC
Code:
i am trying to calculate the SNR for the Ideal ADC model in cadence ahdllib , i know that it should be equal to or around 6.02N+1.76
i have implemeted a code to calculate the FFT of the output of ADC using matlab and i will attach the code
my problem is that i dont know how to calculate the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.