Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
How is skew related to max operating frequency ?
by definition skew is the difference in the clock arrival. So it means with increasing skew there is more time for the data at the capture flop ? In that case it would help setup ?
How to interpret correctly ?
Please let me know.
Thanks ..
Re: CTS----hold
I think eternal has given a good explanation using the equation.
Only after the clock has been routed it will make sense to do the hold timing check as we can now have the actual clock path delay and replace that with the ideal clock.
what is hold time and set up time ?
Anildesh,
You have mentioned the following equation -
Tc-q + Tsetup + Tcskew + Tcomb <= T (setup)
However since clock skew would help meet setup requirement, I believe the equation should be -
Tc-q + Tsetup - Tcskew + Tcomb <= T (setup)
Thanks
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
