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This is the output I got from dc when I executed compile command:
============================================================================
| DesignWare Building Block Library | Version | Available |...
I still have some questions.
1. How do I know how fast my design can run from logic synthesis? From my example, 1GHz clock constraint gives me 0.92 data arrival time, while 2GHz constraint gives me 0.62. They give me different answers, which one should I use to determine the speed of my circuit...
But the difference between 0.92 and 0.4 data arrival time is rather big. And can I do PnR with negative slack? I thought I have to save some room for real clock latency and other physical effect in PnR stage to meet the timing requirement.
Thanks!
Thanks for your explanation. I still have 2 questions.
1. Is it possible to tell DC to try "hard" enough to meet the target frequency, instead of giving up.
2. If my goal is 1GHz, should I use 2GHz in logical synthesis first and use its result for floor planning? Or it really doesn't matter...
Hi,
I tried to synthesize a 64-bit adder. It's pure combinational. When I set the virtual clk to 1GHz. The timing report is
clock vclk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
output external delay -0.10...
I have no clue. This is the tcl script I use for setting up the library
set synthetic_library "dw_foundation.sldb"
set target_library "gscl45nm.db"
set link_library "* $synthetic_library $target_library"
What command should I add that may fix this problem?
Thanks
Hi,
I am trying to synthesize an adder like the one in Sparc T1-cpu.
The code contains two 16-bit adders like the following.
assign {cout16, adder_out[15:0]} = rs1_data[15:0] + rs2_data[15:0] + 1'b0;
assign {cout32, adder_out[31:16]} = rs1_data[31:16] + rs2_data[31:16] + cout16...
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