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Recent content by amir81

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    CFL filckering when turned off

    ptc cfl hi pranam77 (1) switches must be place in phase (hot) line, you know due to dangers of this placement. (2) if i do that, it won't solve it. because the loop already exist. the current pass through the loop (KVL). so this is not the solution thanks Added after 23 minutes: hi...
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    CFL filckering when turned off

    cfl flickering with lamp turned off hi laktronics the resistor for current limiting the neon indicator is about 100~150k. it, at most, sinks about 20mA. this "leakage current" causes this problem. i do not know what is the input impedance of CFL. if it is much lower than 330k, it doesn't work...
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    CFL filckering when turned off

    cfl flashes when off hi pranam77 no. the switch is connected to phase. the neon indicator needs about 1~3mA, but this (AC) current is enough for charging the capacitor and start the ballast. what do you think about using a PTC thermistor?
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    CFL filckering when turned off

    small current when light turned off hi yes. i know it works, but this is not a wise solution. i want to solve the problem.
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    CFL filckering when turned off

    cfl flickers when off hi all recently i changed my old bulb with a new cfl (compact fluorescent lamp). but there is a problem; when i switched off the lamp, it begins to flicker with a time constant of about 2s. i searched for the reason and i found this problem. it caused by a small neon...
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    anyone knows this type of ZNR?

    hi all i attached the image of a ZNR. it is used in a daa part of a modem (for surge/transient protection). i remove it from pcb and the modem now works well, but i know it is not safe. the marking code for this part was "ZNR2" on the pcb. any one knows the meaning of color strips on this ZNR...
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    When should we use bit and when std_logic in VHDL?

    Doubt in VHDL the most important character of std_logic is defined in its resolution table. when you wire (ie: wired and) two signal with different logic level its important to know what is the result. refer to ieee standard for this table.
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    How to derive the factorial of (1/2) ?

    factorial of (1/2) change the variable x=z^2. obtain the new integral and define it i. calculate i^2 . so it will a double integral change the variables of double integral from Cartesian to polar. calculate i^2 . it will be pi. now i=sqrt(pi)
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    How to perform a dither archi for 1-bit sigma-delta adc?

    generally, you can design a random (or pseudo random) sequence generator. you can vary the length of shift register to achieve better results. then add it to your modulator to make your signal busy enough.
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    intialization in VHDL

    as a general rule: initialization of signals (also ports because they are signals) are not synthesizable. neither xilinx nor altera, actel,ql,... support that. however for some fpgas you can use some attributes ( such as init for xilinx fpgas) to initialize ram or lut. but remember fpga...
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    How to Convert from "STD_LOGIC_VECTOR to STD_LOGIC&quot

    convert to std_logic_vector this code will work: process(sclk) is begin if rising_edge(sclk) then count1 <= count1+1; case count1 is when 0 => rd_en <= '1'; -- enable read data from fifo when 1 => sdi <= din(0); -- start reading data and send it to sdi bus(codec) when...
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    Number theory and FPGAs

    you should know some differences between vhdl and programming languages (for example C). when writing a program in C, you don't care how many +-*/ you have. you can compute 784/129. but you have some restriction in vhdl IF YOU WANT TO WRITE A SYNTHESIZABLE CODE. (to download it to an fpga, for...
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    What is the FPGA Advantage ?

    FPGA advantage fpga advantage (fomer renior) is a software packge. it has modelsim, leonardo and precision rtl. you can use these software alone, but with fpga advantage you can manage your (large) design better.
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    Component not found in dXP library (urgent)

    define new pcblib. use some ruler to measure the width and sizes. place pads, tracks, ... and change their properties to the correct ones. save the library. add it to your project.
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    Problem with uninitialized signals when running VHDL simulation on ModelSim

    simulate bidirectional ports modelsim your design should have some components and you use them in your top module. first you should be sure that these components are written correctly. define new projects in modelsim and write testbenches to ensure. i think you might make some mistakes in these...
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