Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I created a BlockRam core using CoreGen. When I instantiate it to ip_image (my instance name), i get the warning :
Instantiating Blackbox module <module_name>.
How do I resolve this error??
I am new to VHDL. Infact, this is my first attempt at writing a code. I wrote the following code for the downsampling of an image in VHDL.
entity downsampling is
Port ( clk : in STD_LOGIC;
din_ip : in STD_LOGIC_VECTOR (9 downto 0);
we_ip : inout STD_LOGIC_VECTOR (0...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.