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Recent content by Alvinnju

  1. A

    who have these two document

    1 DFT Compiler Scan Synthesis User Guide 2 DFT Compiler Test Design Rule Checking User Guide thanks!!!
  2. A

    What are the methods for achieving low power?

    low power design in different levels.it has several different methods in the layout level, using sleep transistor is one method
  3. A

    which synthesis tool are you using?

    i'm using quartus II
  4. A

    HDL Entry vs. Schematic Entry Tool?

    hi i use Verilog,i think it's more easy
  5. A

    Which designer is better: Analog IC or Digital IC?

    Which one is better? Digital IC designer who know Analog IC design better
  6. A

    another question -----high speed adc

    pipeline is a good choice.
  7. A

    DC_Balance: Manchester-coded data and 8b/10b coding

    dc_balance 8b10b coding--maps 8bits value to 10-bits codes. It guarantees a minimum frequency od 0/1/0 transition within the coded data stream,enabling reliable recovery of the serial bit clock at the receiver and guaranteeing an average DC value of 0 across the data stream. It's a robust...
  8. A

    Where can I get the "HDL Chip Design" book by Smith?

    HDL Chip Design book fortunately find the book
  9. A

    Quartus® II Web Edition

    web edition need checking the online state?? I used well
  10. A

    Help: asynchronous FIFO design!

    asynchronous fifo design The read comarator compares the value of the read and write flags associated with the second-next read-pointer position.The FIFO empty is set if the flags have the same value.similarity,the FIFO full is set if the fread and the second-next write-pointer position have...
  11. A

    A problem when i learn to use nios

    When I use the SOPC Builder(quarters4.2) to do System Generate,the error happen. no install.ptf file found at d:/altera/quartus42/sopc_builder/bin/europa/europa_utils.pm line 1756. Please give some advise ,thanks!!

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