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Hi,
I'm going to work on I2C IO buffer, analog part.
There is a requirement of 50ns/ 10ns glitch filter on the input filter.
I want to know
1) from where this glitch originated ?
2) Whats specific about 50ns/ 10ns ?
3) why this glitch filter spec is not there in other IOs ?
Thanks.
paper request
B. Sekerkiran, “A Compact Rail-to-Rail Output Stage for CMOS Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, vol. 34, pp. 107-110, 1999.
ADC: Max error
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It is always commented that this error has to be less than 0.5LSB
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