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Recent content by alok_ky

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    Help me understand a CDM ESD protection

    Re: esd cdm protection circuits Yup..... What happens if substrate acquires positive charge ?
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    i2c driver glitch filter

    Hi, I'm going to work on I2C IO buffer, analog part. There is a requirement of 50ns/ 10ns glitch filter on the input filter. I want to know 1) from where this glitch originated ? 2) Whats specific about 50ns/ 10ns ? 3) why this glitch filter spec is not there in other IOs ? Thanks.
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    paper request- A Compact Rail-to-Rail Output Stage for CMOS

    paper request B. Sekerkiran, “A Compact Rail-to-Rail Output Stage for CMOS Operational Amplifiers”, IEEE Journal of Solid-State Circuits, vol. 34, pp. 107-110, 1999.
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    ADC: Max error - where this 0.5 LSB limit originated ?

    ADC: Max error Hi I noted that, in an ADC, when some inaccuracy creates any error, then this error is compared with the +/- 0.5 LSB value. It is always commented that this error has to be less than 0.5LSB From where this 0.5 LSB limit originated ? Will all the ADC errors not get added to...
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    low power delta sigma

    tutorials on delta-sigma modulators It does not exist at the above mentioned link, anymore. Can somebody upload this book ?
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    need these ieee papers - related to adc testing

    Can anybody upload these papers ? I also need them.
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    Question about MOSCAP and the depletion region

    Hi, When the capacitance of a MOS is measured at high frequencies (assuming it is biased), then no inversion layer is generated, as there are no minority carriers (Assume that gate is biased positive and semiconductor is p-type). Then to compensate for the +ve voltage on the gate of the cap...
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    What is a tip implant?

    Can anybody tell me, what is "tip implant" ????
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    Need Statistical Modeling for Computer-Aided Design of Mos

    book request I need the above mentioned book...urgetnly....can anybody upload it ?????
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    Need Statistical Modeling for Computer-Aided Design of Mos

    book request Statistical Modeling for Computer-Aided Design of Mos Vlsi Circuits By Christopher Michael, Mohammed Ismail
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    Question about Fermi Levels at equilibrium

    Fermi Levels Analog Guru's thinking is the same as mine. Can somebody help me understand this fermi level doubt ???
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    Question about Fermi Levels at equilibrium

    Re: Fermi Levels If the workfunctions are different for the metal (say Al) and silicon, then How come the fermi levels become same at equilibrium. I know that band bending happens and make the fermi-leveals same ? What causes the bands to bend and make the fermi levels equal, when no current...
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    Question about Fermi Levels at equilibrium

    Hi, I know that in a pn junction, at equalibrium, the Fermilevels in the p and n sides reach the same level, because the elcetron will flow from both sides to the other side, untill the fremi - levels become equal. Now, I want to know, as to why, at equilibrium, the fermi levels in the metal...
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    Are the DFM guidelines given by the foundry?

    Re: DFM? Any papers/ books related to DFM are required. Added after 24 seconds: Any papers/ books related to DFM are required.

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