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Recent content by alkaios

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    [SOLVED] extract non-standard number of LS bits from std_logic_vector in vhdl

    i just did it, and it worked! thank you very much! you saved my day :)
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    [SOLVED] extract non-standard number of LS bits from std_logic_vector in vhdl

    thank you for your immediate response. unfortunately i can't understand you completely. could you be more specific? for example, in for loop the desired iteration range should be x, how would i make it constant, and how this would be helpful? (value of x is computed in another component and...
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    [SOLVED] extract non-standard number of LS bits from std_logic_vector in vhdl

    hello! i have a problem in vhdl and i hope you can help me i want to take LS bits from a signal, but the number of these bits it's not certain. to be more specific, i want to do this: a <= b(x-1 downto 0). a, b, x are std_logic_vectors. x is calculated somewhere else in my program. range of...
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    [SOLVED] right logical shift /different width between input and output

    i didn't know the function resize. i found out how to use it, and got my desired result. thanx a lot.
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    [SOLVED] right logical shift /different width between input and output

    i want to implement the following operation in vhdl: x(52:0) = y(23:0) >> z (>> is the logical right shift) value of z is not standard, it's the result of a substraction and it can change. i already tried operator srl and function shift_right but they don't work because of the different...
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    arithmetic shift and latches in vhdl

    thank you! finally i understand this message! so, in other words, there is nothing different that i can do with my code and my design won't have problems because of that. right?
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    arithmetic shift and latches in vhdl

    i don't understand what i do wrong. i initialize xreduce inside the architecture: signal xreduce : std_logic_vector (12 downto 0) := "0000000001000"; with a simple testbech, the design looks that it works fine. LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; USE...
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    arithmetic shift and latches in vhdl

    hello :-) I want to ask: does shift arithmetic always creates latches in vhdl? Is there any way to prevent this from happening? Should I or should I not care about these latches? Here's my code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; use...
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