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Recent content by alicia8283

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    fully differential op amp simulation

    differential op amp Thanks a lot. Do you have any reference on the test bench?
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    fully differential op amp simulation

    op amp simulation Then how should we actually simulate for whole system ( fully diff amp togather with the CMFB) if the CMFB is switch cap type? i read from this forum that we have to use spectreRF to simulate it, but how if the cadence tools i used do not have spectreRF license? Do we have...
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    Please help me on this reference circuit..

    hi guys, Thanks a lot for your reply. hi Allan_guo, could you explain further how MNN1 used for startup? and more detail explanation on MNN2 to reduce system error? Initially i thought MNN2 is as startup circuit for this bandgap. hi jianjing526, nanch3 is native transistor and no...
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    Please help me on this reference circuit..

    hi, could anyone please help to explain the operation of the circuit? i am much appreciated.. thanks
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    Substrate charge pump basic cell design

    cmos substrate pump hi, i also want to know which parameters would affect by the currrent loading for the charge pump. thanks!
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    Please help me on this reference circuit..

    hi all, could anyone please explain to me the operation of the circuit below? i know this is a bandgap but i confuse for the part Q3, R and why there is a cap. Q1=8Q2 Thanks a lot first. :D another question is, what is the difference between model "nanch3" with "nch3" for TSMC .18u process?
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    Which is the best book about CMOS design fundamentals?

    cmos books written by -razavi -p. allen -grey meyer this 3 books is the books that people normally read for fundamental.
  8. A

    vddio power line width

    Normally will be roughly 1um width for 1mA. So how big is your current?
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    pass the commands from VC++ program to the command window i

    cadence skill script help This is the lab manual for the Skill language from cadence. Hope it helps
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    How to know whether the threshold voltage of POR is ok?

    I m using TSMC .18um process, currently simulate on a POR, the threshold voltage is around 1.214V. As the output POR will go in to some logic gates (DFF and inverter), so it is important to know whether this Vthreshold is able to let the logic regconized as logic "high" or not. I found online...
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    Problem about POR(power-on reset)

    hi.. As what i understand, the POR block will be connected to some flops or other digital blocks, so the Vthreshold of POR block is important to make sure it will be higher than Vih of the digital circuit which connected to POR. Please correct me if i make mistakes. i would like to ask, the...
  12. A

    How to test the CMRR of a fully differential amplifier?

    worst cmrr anyone could tell me is it anyway i able to get those scripts and test schematic in the white paper " Functional Verification Of A Differential Operational Amplifier" ?? thanks in advance
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    high swing current mirror?? please help me ..

    vds of a diode connected transistor really thank you everybody for the explanation :)
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    how to reduce offset for the op-amp in a LDO?

    how to reduce offset i have an op-amp which is used for LDO. the Vref is about 1.16V. At that point, my op-amp's offset is ~6mV will this a problem for my LDO? How to lower the op-amp offset? my op-amp is only one stage op-amp which using high swing cascode current mirror as load current...
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    how to obtain good PSRR for two stage amplifier?

    ahuja psrr how to obtain good PSRR for two stage amplifier? My stability is ok as i have put compensation cap at the 2nd stage.. thanks in advance..
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