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Recent content by Alexwonglik

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    Cycling LED projects advice on Atmega2560

    Hi, I am writing a program to cycle LEDS using push button on STK600 powered by Atmega 2560. Two cases Case 1: No button pushed - cycle LEDS all the way through Case 2: Button pushed - cycle LEDS up to the button pressed I use timer0 for delay in the design and Port B as output while Port...
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    Transfer the ASCII Value to Digilent Basys 3 FPGA board

    Thanks for the guide. I have revised the design.
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    Transfer the ASCII Value to Digilent Basys 3 FPGA board

    Hi, thanks for the reminder. Actually, I got the following warnings in the synthesis at the top module. It is about the transmitter module instantiation. I wonder what port I should connect to "data" input in the transmitter. Physically, I want the ASCII value of the keystrobe can be shown in...
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    Transfer the ASCII Value to Digilent Basys 3 FPGA board

    Hi, I want to learn how to use communicate the FPGA with RS232, so I tried to create a project - whenever I hit the keystroke, the 8 bits LED will show the ASCII value. The hardware I used are Basys 3 and Pmod RS232. I can successfully generate the bit file and load that to Digilent Basys 3...
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    Invalid outside of .subckt in Pspice

    Hi, thanks for the tips. It works now.
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    Invalid outside of .subckt in Pspice

    I have tried various way to solve an error in Pspice --> ERROR(ORPSIM-16101): Invalid outside of .SUBCKT Here is the circuit file. Can anyone suggest some hints? .SUBCKT opamp 1 2 3 *node 1: output terminal *node 2: non-inverting input terminal *node 3: inverting input terminal Eopamp 1 0 2...
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    Stop Watch on Xilinx FPGA board Verilog

    Hi thanks for the advice. For the first one, it is required and provided in the project assignment. The second one yes thanks I will pay attention to the denouncing. The reason I used nested if to check the lsb to msb one by one. That is the only way I can think of. It will be great if there is...
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    Stop Watch on Xilinx FPGA board Verilog

    Hi I tried to use verilog to develop a stop watch on a fpga board seven segment display. It doesn't count correctly (See the video: https://www.youtube.com/watch?v=uHqJeKxjPrA) I guess the problem is from the counter.v and top.v? However, I can't figure what's wrong with the code. Hopefully...
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