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Re: process variation
To make on chip variation minimum, you should use both stage match and metal match. For hold time check, you can use fast data and slow clock for back-annotated SDF.
(1)size up=> if PR congestion, then
(2)change logic=> doesn't work, then
(3)make latency of CLK=>doesn't work, then
(4)make more pipeline stages=>doesn't work, then
(5)re-coding
In 16M gate count chip consuming 10W, how much percentage fillers should be swapped by decoupling cap? Is there any math equation to show the mechanism? where can find the reference document?
Thanks
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