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Recent content by Alauddin123

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    Input and output delay values for FPGA

    Hi All, I have been working on FPGAs and know that how important I/O delays are in order for the device to work in external environment . But to assign its value i have found like some people prefer input delay as 75% of clk_period and output delay as 25%. What is actuall logic behind this ...
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    clocking issues in capturing debug signals in ILA

    thanks to you all.. I figured out the problem. I had the reset pin connected to MMCM so the output clock from MMCM was not free running. After i removed it , its working fine.
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    clocking issues in capturing debug signals in ILA

    Hi All, i have a design which has 125Mhz Ip clk coming from onboard oscillator. I then generated many frequencies(div2,div4 etc) using MMCM_ADV for different modules. Now i wanna probe the signals in each module and see them in logic analyzer. But tool is throwing error like the clock for...
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    what pins The programming USB-jtag port and 8 pin JTAG header is connected to FPGA?

    Hello Everyone, I have many FPGA development/platform boards that can be programmed/configured by the USB-JTAG port available and also has a JTAG 8 pin connector too. 1) why do we have two when we can program and get debug signals using same USB-JTAG port(It can be done in ZYBO(zynq board) ...
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    Dual flop synchronizers and mtbf

    I started reading on dual flop synch and i found like for metastable data to settle , we add dual flop to give once cycle time to it. my question is "After the first edge If the first flop goes metastable and settles to an incorrect value, then it will be propogated on flop 2". 1) How to...
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    OSERDES implementation and connections

    Hi All, I am new at designing and implementing serdes in design. I have a high speed data stream to send at high bit rate(working on zynq ultrascale), so i need to implement a OSERDESE3 for that. i need to know the following. 1) what is Gearbox and why it is needed and how will i...
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    Pipeline stages regs

    Hello All, I came across the option of adding register pipeline stages(1,2,3) while generating the BRAM IP via coregen. can any one explain me in detail how this additional regs improve the performance of the core ?
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    Usage of HP and HR IO banks and their selection

    Hi... I wanna know a lot about HP and HR IO banks and there selection and there usage.their significance and their contstraints. In UG471 its not that clear. with regards Mohammed Alauddin
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    FPGA timing due to Dist ram

    Hi all, I am working with prototyping. I am getting a lot of timing violation due to Ram getting inferred as 150 Dist rams. I made it block ram but still the issue is my design has asynch read and reads the data as soon as raddr gets updated, but Bram has got synch read and waits till next...
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