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consider a memory map which has address A[0:15]
and data bus as D[0:7];
and during mapping A[3] and A[4] are interchanged inside DUT so complete address range will be different.
write at Add = 0008h, the write will actually will happened on address 0004h consider that data is D
during read...
Hi,
If i have one situation where my Address bus A[0:15], A[14] and A[13] are interchanged in the address mapping. how can i verify this bug.
Due to this mismatch complete Address mapping will change but as read and write on the given address will be fine. and will not give any error on any...
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