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Recent content by akkafrawy

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    PSS analysis problem with Verilog-A and hidden states

    Hi everyone, I want to simulate the effect of mismatch and process variation on the system performance of my SAR Analog to Digital Converter. The system now is simply ideal system with only one transistor level block, the other blocks are written in Verilog-A code in Cadence-Spectre. The...
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    Error in Cadence noise analysis

    Hi everyone, I am desiging a current to voltage converter, I have this error in Cadence when I am simulating the noise, I want to see the noise summary (integrated noise from 1 Hz to 500 MHz) but the error I got is: "ERROR (PRINT-1011): No device type is selected for generating the noise...
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    Tracking Successive Approximation Register ADC

    hi everyone, I would design a sar adc which has its output tracking its input, any idea how to build the sar logic, please post the flowchart or the veriloga code?
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    Linearity of MOS transistor_the meaning

    Unfortunately, I don't have ref., but i heard it a lot in many lectures
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    Linearity of MOS transistor_the meaning

    Hi, can anyone tell me what does " a 10 bit linearity can be extracted from 90nm CMOS transistor" mean? how is it related to the Ids-Vgs of such a transistor? Has it a relation to the dynamic range?...any info, thx
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    Sar adc _ using sample and hold block in sar adc and keep tranking with input signal

    Hi everyone, I am confusing how would I sample and hold the input signal in my SAR ADC and keep the tracking property between the input and output at the same time, I understand that either sampling the input and hold it for 6 clk cycles (in case of 6 bits) until the digital output appears or...
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