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Hi everyone,
I doing a mini project for SOC. I am designing a vechicle speed controller using Verilog and synthesis using Leonardo Spectrum. Then, the schematic is generated to layout by using Design Architect.
During my progress in ic station, i create a new cell for the layout and using...
Hi,
I am using modelsim. I would like to hook up non input/out signal to testbench from design unit.
Example
Design unit:
module design_unit( out1, out2, in1, in2);
input in1, in2;
output reg out1, out2;
.......
reg [5:0] int_reg;
......
endmodule
Testbench unit:
module...
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