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Recent content by Airbag79

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    Power Aware Signal Integrity Analysis of SerDes and DDR4 Interfaces.

    SERDES is not as sensitive to Common-Mode Noise due to differential topology. It's more critical in DDRx application because data is single-ended and there is a a lot of SSN. Albeit, it's never a bad thing to incorporate non-ideal Power and GND in your simulations, as it will be more accurate.
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    Propagation Delay calculation

    Best way to get propagation delay is unwrap the phase of S21 (Insertion Loss) and plot the flight time. Otherwise, it is Speed of light divided by the square root of the effective permitivity of the transmission line/material. Keep in mind effective Dk of vias can be 2-3 x slower than...
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    [SOLVED] HFSS 3D Layout - Define PCB Differential Waveports

    What is the error? Also, layer 4 is a poor return current path, as your return current will be constrained to L3 and L1.
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    S11 inductance measurement

    Here is a screen shot of my ADS workspace. Shows all three plots and equations.
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    S11 inductance measurement

    Because that is the Reactance/Inductance. The real part is the resistance.
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    S11 inductance measurement

    If you have ADS. Use ZIN function to derive impedance, then divide the imaginary component of the resultant impedance by 2*pi*f (frequency point of impedance).
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    is there any issues with gold wire bonding on die aluminum bond pads

    Electromigration can be an issue if current densities are high enough, due to lattice diffusion at intermetallic junction.
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    current density in analog layout

    Are you inquiring what the max allowable current density for a given material like copper?
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    Ddr4 data lines routing

    I wonder why...Your assumption of absolutes and only considering single variables is misleading. I'm not attempting to pontificate with you, only augment the fact that oversimplifying complex topics is ambiguous.
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    Ddr4 data lines routing

    Again, this is simply not true. It depends on numerous variables. - - - Updated - - - Any common-mode signal above 1 MHz that encounters a return plane void will generate substantial XTALK in addition to poor Return Loss, irrespective of edge-rate (relatively speaking). Edge-rate is more...
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    Ddr4 data lines routing

    1.) If you're under 1 GHz, you may be able to get away with routing on VDDQ and VSS. Albeit, if you share VDDQ and VSS as reference planes for a stripline TL, the only path for the return-current is the through the VDDDQ-VSS (plane plane) impedance. This will generate ground bounce, since...
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    Lossy Stripline/Microstrip Filters at UHF

    When you say "extremely high losses" can you elaborate on the magnitude of losses in dB at the frequency of interest? The majority of insertion loss occurs from conductor losses, not dielectric losses. Unless you're utilizing a very lossy material with poor Df. Also, it's very important to have...
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    Decouple Cap selection for analog circuit

    Actually, wrt ESR and PDN/Z impedance you typically want more ESR to quench any modal peaks that exist in your frequency band. The R dampens/flattens the magnitude of the modal peak to bring down the PDN impedance at that frequency. OP: You really need to perform a PDN analysis in the...
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    HFSS Airbox size and fabricated antenna measurement results

    I typically default the extents to 0.015, for both vertical and horizontal padding. This will also reduce simulation time substantially.

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