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Recent content by ahyuanz

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    help with vhdl coding

    i just compiled and it pass, but will it work? entity MUX is Port ( EN : in STD_LOGIC; A_IN : in STD_LOGIC; B_IN : in STD_LOGIC; C_IN : in STD_LOGIC; D_IN : in STD_LOGIC; RES : in STD_LOGIC; MUX_OUT : out...
  2. A

    help with vhdl coding

    how to i write for 4input (a,b,c,d) and merge into 1 output with 4bits with 'a' as the msb and 'd' as the lsb
  3. A

    design feasibility for spartan3 board

    Hi all, is it possible to design a project using spartan3 board simulating reading from data from a ram/rom and displaying how much space is being used?
  4. A

    Need Help in compiling VHDL using XILINX ise 9.2i

    sorry for troubling you guys. My intention was to actually use 'set' to manually increase the value in the counter using a push button, that is why i use edge trigger. So can it still work the way i want it to if i follow the code palai_santosh suggest by using logic 1 or 0 ?
  5. A

    Need Help in compiling VHDL using XILINX ise 9.2i

    Really appreciate if who could help me here is the problem : My project is to create a stopwatch. The syntax is ok. However, when i am creating timing constraints... it fails to synthesize and prompt me this error : Signal MOD10CARRY_temp cannot be synthesized, bad synchronous description...
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