Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
thx you, montage and eng_semi.
i'm a beginner of anlog ic design.i still have a little confused about this problem.
the vccs and gds are series with C1 and Cgs.so is the circuit's small signal diagram shown below right?if i get 3 equations from the node A,B,C using KCL and try to resolve it,i...
in the circuit,C1>Cgd.but i still want to get the exactly equivalent capicitance at the output of c1.
now at the higher frequency as you said(like :10Mhz),does the C1 still shorted when C1>Cgd?
I think i can take the NMOS as an network about cap-res to caculate the equivalent cap.but i'm...
hi,everyone
1. there is a cap C1 as depicted in the attachment picture.it's connected to the gate of the NMOS M1.now,i want to know how can i get its equivalent capacitance at the output node.
2. i want to get a simulation result about f-V curve of a VCXO.how can i get it?
thx
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
