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Why do you care about the linearity of the inverters? I guess it is important they switch at the voltages you listed. If you apply higher voltage, for sure they will still switch...The same if you apply lower input voltage, they will not switch. I hope I didn't misunderstand your point..
Dear all,
does anybody know how to run a multithred (using all cores of the server) simulation? I use the option: option( 'multithread "on" ) but I notice that the simulation uses lower resources from the server than when I run the multithread simulation using spectre from the ADE. Is there any...
Dear all,
I have a problem with the postlayout parasitic extraction in calibre. My design kit recognizes only scaled sizes of transistors, that is, if a 0.5um width transistor is needed I have to put 0.5 instead of 0.5u. The design kit model is scaled by 10^-6. My problem is now with the...
Hi all,
I have a problem when I try to run ocean simulations with my technology. The problem is that in schematics I have to put the size of the transistor without adding "u" or "n" (indicating micro or nano). If I add u or n, it will show an error. E.g. if I want a mos with length 400n I have...
Have you taken into account the extra load added by the comparator? And the kickback effect of the same? You might try to add a preamplifier in front of the comparator to reduce the kickback effect if that is causing any trouble to your modulator...
It depends on noise, power consumption, heating..Typical output capacitance is around 10pF. Use class AB buffer and you get something like hundreds of MHz speed.
1. Digital pads have digital buffers (inverters) to interface the off-chip electronics with the core. No analog signals can thus pass through a digital buffer
2. Power supply pads have ESD protection circuitry and must allow the flow of large currents. They are usually bigger in size
3. Usually...
Dear all,
I designed an IC chip. I am preparing the test setup at the moment. The difficult task will be the generation of patterns to control all the functions of the chip. I need more then 30 different control signals (syncronised to the main clock). I have an FPGA board. Can anybody tell me...
Sorry for being late, I didnt have access to my design.
1) I measure the DC gain by parametric analisys by changing one of the imputs amplitude by a few mV and see the difference at the output.
2) I clock at 500MHz. The unity gain bandwidth of the opamp is now ~1GHz.
Here is the settling of the...
All transistors are in saturation with or without SC-CMFB. And the gain at DC shouldnt change if I add SC-CMFB. Strange...And I also get a ripple at the output when I apply a differential signal at the input. Is that normal?
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