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Recent content by adityarajrulz

  1. A

    Path & pathSeg difference

    Could anyone please tell me the difference between WIRe, PATH and pathSeg in general and in respect to virtuoso layout ? Thanks, Aditya
  2. A

    virtuoso pIn access and instTerm

    Hi, in respect to cadence virtuoso tool, what is the significance of pin access field option in the properties of any Pin. What exactly is an instTerm, ( I have heard that virtuoso router looks at instTerm for routing but have no idea about instTerm )
  3. A

    Batch checker environment variable in virtuoso

    Any idea as, what are and where can i find the environment variables for the BAtch checker form, in virtuoso ? like for VERIFY -> DESIGn->ROUTABIliTY environment variables !!! the general path would do... /dfII/samples __________ Thanks
  4. A

    pin dimension in virtuoso layout

    i am using 45 nm tech file in virtuoso layout. In the tech file the constraint for Metal1 is , minWidth = 0.06 and minArea = 0.02. If i draw a pin with Metal1 , do the same constraint apply to pin also, or are they applicable to only rectangle or any shape ? Because according to these...
  5. A

    how to transfer a row of 2 d array into a 1 d array

    I have a 2 d array : type memory is array(0 to 100) of std_logic_vector (7 downto 0) now i want to read a row of this "memory" array where the row number is known to me in terms of binary values say a1,a2,a3,a4,a5,a6.. i have to read the particular row corresponding to the address...
  6. A

    how to introduce a delay/wait signal in parameter sensitive process in vhdl

    I have a code simulating a flash memory where it receives a reset signal, and after receiving that signal it starts working only after a particular time "reset time = 200 ns" if before the end of this 200ns the reset signal comes again then the 200ns need to be reconsidered and the "reset...
  7. A

    refer any memory location in terms of variables.

    thanks for your earlier help. Due to some reason , I am switching over my code from Verilog to VHDL. Can you kindly help me as to how to do this because syntax like array({b1,b2,b3,b4}) doesnt seem to work!!!!!.
  8. A

    refer any memory location in terms of variables.

    i have a memory element as : reg [7:0] memory [0:1000] with data fed into the memory after reading from a .bin file . if i have to read any memory location say i. location no 3 , then i can do it by writing memory[3] or memory[2'b11] ii. location no 15 as memory [15] or...
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