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Thank you, that sums it up.
I meant something much simpler. just to select the "short" reg range.
I know how to code it using local parameter:
localparam SHORT_LEN = 6;
reg [10:0] long;
reg [SHORT_LEN-1:0] short;
//imagine always block:
short <= long[SHORT_LEN-1:0] //WORKING!
But I don't want...
The input variable width part of the example indeed has nothing to do with VHDL attribute, but this feature together with the VHDL attribute used later when declaring the counter signal, creates generic module without passing any additional information. (the compiler will auto-generate all the...
Thank you,
So like I thought, there is not a exact equivalent.. Eventually you'll have to create another code instance (define/param/local param) to support generic code.
What if simply want to do something like:
reg [10:0] long;
reg [5:0] short;
//imagine always block:
short <= long[short:0]...
Hi,
VHDL has a powerful feature called attributes. Using attribute I can generalize modules quite easily, for example:
entity alaram is
port(
clk : in std_logic;
reset : in std_logic;
CountTo : in std_logic_vector;
CountEn : in std_logic;
Done : out std_logic);
end alaram ;
architecture...
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