Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Dear VHDL-AMS expert,
I need an advice for the following codes for transmission line model example. I can compile it, but i will not get any result. Something missing perhaps
.........................................................
entity transmission_line is
port (terminal a,b,g ...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.