Hamster VHDL-AMS transmission line example

[abra]

Dear VHDL-AMS expert,

I need an advice for the following codes for transmission line model example. I can compile it, but i will not get any result. Something missing perhaps

.........................................................
entity transmission_line is
port (terminal a,b,g : electrical);
end entity transmission_line;

architecture bhv of transmission_line is
constant Lz : real :=1.0;
constant Cz : real :=1.0;
constant Lenght : real :=1.0;
constant N : real :=5.0;
constant dz : real :=Lenght/N;
constant C : real :=Lz*dz;
constant L : real :=Cz*dz;
constant Zs : real :=1.0;
constant ZL : real :=1.0;
constant Vs : real :=5.0;

quantity Vin across Iin through a to g;
quantity Vout across Iout through b to g;
quantity V1,V2,V3,V4 : real;
quantity I2,I3,I4,I5 : real;

begin

-(V1-Vin) == L*Iin'dot;
-(I2-Iin) == C*V1'dot;
-(V2-V1) == L*I2'dot;
-(I3-I2) == C*V2'dot;
-(V3-V2) == L*I3'dot;
-(I4-I3) == C*V3'dot;
-(V4-V3) == L*I4'dot;
-(I5-I4) == C*V4'dot;
-(Vout-V4) == L*I5'dot;
-(Iout-I5) == C*Vout'dot;

end architecture bhv;


and, when I add inteface condition, I will get "too many equation, ambiguous model".

Vin == Vs - Iin*Zs;
Vout == Iout*ZL;

Thanks in advance

 

[vibhu.jiit]

Hello dear.........
Actually this program is an example of transmission line given in an IEEE paper of Nikitin and is incomplete.
Attach a source voltage of step response and 2 resistor model, one as source (Zs) and another as load (Zl) and write a test bench to port map these component.
You can take help from hAMSter examples for voltage source and resistor model and port mapping. Do not declare voltage source as a digital source, it should be defined as "ELECTRICAL".
Actually in your code there is a problem of generating a source voltage of constant amplitude with respect to time and attaching it with electrical transmission line.
Try it yourself and then reply me, if can't simulated i will give you the whole code of this in hAMSter as well as of SMASH too.

Do you have SIMPLORER of ANSOFT? It is much better than hAMSter.

Thank you....

Dear VHDL-AMS expert,

I need an advice for the following codes for transmission line model example. I can compile it, but i will not get any result. Something missing perhaps

.........................................................
entity transmission_line is
port (terminal a,b,g : electrical);
end entity transmission_line;

architecture bhv of transmission_line is
constant Lz : real :=1.0;
constant Cz : real :=1.0;
constant Lenght : real :=1.0;
constant N : real :=5.0;
constant dz : real :=Lenght/N;
constant C : real :=Lz*dz;
constant L : real :=Cz*dz;
constant Zs : real :=1.0;
constant ZL : real :=1.0;
constant Vs : real :=5.0;

quantity Vin across Iin through a to g;
quantity Vout across Iout through b to g;
quantity V1,V2,V3,V4 : real;
quantity I2,I3,I4,I5 : real;

begin

-(V1-Vin) == L*Iin'dot;
-(I2-Iin) == C*V1'dot;
-(V2-V1) == L*I2'dot;
-(I3-I2) == C*V2'dot;
-(V3-V2) == L*I3'dot;
-(I4-I3) == C*V3'dot;
-(V4-V3) == L*I4'dot;
-(I5-I4) == C*V4'dot;
-(Vout-V4) == L*I5'dot;
-(Iout-I5) == C*Vout'dot;

end architecture bhv;


and, when I add inteface condition, I will get "too many equation, ambiguous model".

Vin == Vs - Iin*Zs;
Vout == Iout*ZL;

Thanks in advance

 

[fardeen123]

Dear Sir,
Iam working on a project with developng impedence matching models in AMS for connectiing behavioral level models and i need to implement the same transmission line example .I have generated the testbench and still getting some errors ..Kindly guide me as to where my code i s erreneous. Iam attaching the code.
LIBRARY DISCIPLINES;
LIBRARY IEEE;
USE DISCIPLINES.ELECTROMAGNETIC_SYSTEM.ALL;
USE IEEE.MATH_REAL.ALL;
entity transmission_line is
port (terminal a,b,g : electrical);
end entity transmission_line;
architecture behav of transmission_line is
constant Lz : real :=1.0;
constant Cz : real :=1.0;
constant Length : real :=1.0;
constant N : real :=5.0;
constant dz : real :=Length/N;
constant C : real :=Lz*dz;
constant L : real :=Cz*dz;
constant Zs : real :=1.0;
constant ZL : real :=1.0;
constant Vs : real :=5.0;
quantity Vin across Iin through a to g;
quantity Vout across Iout through b to g;
quantity V1,V2,V3,V4 : real;
quantity I2,I3,I4,I5 : real;
begin
-(V1-Vin) == L*Iin'dot;
-(I2-Iin) == C*V1'dot;
-(V2-V1) == L*I2'dot;
-(I3-I2) == C*V2'dot;
-(V3-V2) == L*I3'dot;
-(I4-I3) == C*V3'dot;
-(V4-V3) == L*I4'dot;
-(I5-I4) == C*V4'dot;
-(Vout-V4) == L*I5'dot;
-(Iout-I5) == C*Vout'dot;
Vin == Vs-Iin*Zs;
Vout == Iout*ZL;
end;
---------------------------------------------------------------------

LIBRARY DISCIPLINES;
LIBRARY IEEE;
USE DISCIPLINES.ELECTROMAGNETIC_SYSTEM.ALL;
USE IEEE.MATH_REAL.ALL;
entity resistorsimple is
generic(res:real:=1.0 );
port(terminal p,n: electrical);
end entity resistorsimple;
architecture behav of resistorsimple is
quantity vr across ir through p to n;
begin
vr == res*ir;
end;
--------------------------------------------------------------
LIBRARY DISCIPLINES;
LIBRARY IEEE;
USE DISCIPLINES.ELECTROMAGNETIC_SYSTEM.ALL;
USE IEEE.MATH_REAL.ALL;
ENTITY voltsourcenew IS
generic( amp:real:=1.0);
PORT( TERMINAL p,m : electrical);
END voltSource2;
ARCHITECTURE behav OF voltsourcenew IS
quantity V_volt across i_volt through p to m;
BEGIN
V_volt ==amp;
END;
------------------------------------------------------------------
LIBRARY DISCIPLINES;
LIBRARY IEEE;
USE DISCIPLINES.ELECTROMAGNETIC_SYSTEM.ALL;
USE IEEE.MATH_REAL.ALL;

ENTITY testbench_examp1e_1 IS
END ;
ARCHITECTURE behav of testbench_examp1e_1 IS
TERMINAL n1,n2,n3: ELECTRICAL;
BEGIN
Vs: ENTITY voltsourcenew(behav)
GENERIC map (amp => 1.0)PORT map (p => ELECTRICAL_GROUND, m => n1);
RS: ENTITY resistorsimple(behav)
GENERIC map (res => 50.0)PORT map (p => n1, n => n2);
TR: ENTITY transmission_line(behav)
GENERIC map (Length => 0.5, L => 250.0e-9, C => 100.0e-12, N => 50)PORT map (a => n2, b => n3, g => ELECTRICAL_GROUND);
RL: ENTITY resistorsimp1e(behav)
GENERIC map (res => 50.0)PORT map (p => n3, n => ELECTRICAL_GROUND);
END;
------------------------------------------------------------

These are the errors iam getting
C:\Program Files\Hamster\Examples\test files\TL test.vhd( 5,ENTITY transmission_line) : Info : Entity/Package "transmission_line" overwritten

C:\Program Files\Hamster\Examples\test files\TL test.vhd( 43,ENTITY resistorsimple) : Info : Entity/Package "resistorsimple" overwritten

C:\Program Files\Hamster\Examples\test files\TL test.vhd( 57,ENTITY voltsourcenew) : Info : Entity/Package "voltsourcenew" overwritten

C:\Program Files\Hamster\Examples\test files\TL test.vhd( 72,ENTITY testbench_examp1e_1) : Info : Entity/Package "testbench_examp1e_1" overwritten

C:\Program Files\Hamster\Examples\test files\TL test.vhd( 82,ARCHITECTURE behav OF ENTITY testbench_examp1e_1) : Error : Local "length" is not existing

C:\Program Files\Hamster\Examples\test files\TL test.vhd( 82,ARCHITECTURE behav OF ENTITY testbench_examp1e_1) : Error : Local "l" is not existing

C:\Program Files\Hamster\Examples\test files\TL test.vhd( 82,ARCHITECTURE behav OF ENTITY testbench_examp1e_1) : Error : Local "c" is not existing

C:\Program Files\Hamster\Examples\test files\TL test.vhd( 82,ARCHITECTURE behav OF ENTITY testbench_examp1e_1) : Error : Local "n" is not existing

C:\Program Files\Hamster\Examples\test files\TL test.vhd( 84,ARCHITECTURE behav OF ENTITY testbench_examp1e_1) : Error : Cannot save/load file "C:\Program Files\Hamster\VHDL_Work\\resistorsimp1e_ent\resistorsimp1e.entity_bin"

C:\Program Files\Hamster\Examples\test files\TL test.vhd( 84,ARCHITECTURE behav OF ENTITY testbench_examp1e_1) : Error : Local "p" is not existing

C:\Program Files\Hamster\Examples\test files\TL test.vhd( 84,ARCHITECTURE behav OF ENTITY testbench_examp1e_1) : Error : Local "n" is not existing

C:\Program Files\Hamster\Examples\test files\TL test.vhd( 85,ARCHITECTURE behav OF ENTITY testbench_examp1e_1) : Error : Simulation object for entity testbench_examp1e_1 not created because of 7 errors

C:\Program Files\Hamster\Examples\test files\TL test.vhd( 88,???) : Error : Compile/link failed because of 7 errors <Tue Feb 07 20:27:53 2012
>

C:\Program Files\Hamster\Examples\test files\TL test.vhd(???,?] : Error 70015 : error with compiling
Kindly help me sir.It will be a big help if you can send me the simplorer code as well sit Thanks in advance.my mail id is mailtoahmed@gmail.com or you can post it here sir.Thank you