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Recent content by AbinayaSivam

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    itoa Function in C: How to read all DestinationBuffer values (int) into String Forma

    Modified code but even i am unable to read the data in Hercules. I am working with Xilinx Ethernetlite (LWIP) design. I am able to transfer the data from KC board to PC (Hercules) through Ethernet only if buf =32. But my actual buffer size is 1024. How to increase the buffer size from 32 to...
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    XilinX LWIP : Whether Ethernetlite design can be implemented without using AXI UART

    I have gone through the document. Any example design please. Thanks
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    itoa Function in C: How to read all DestinationBuffer values (int) into String Forma

    Re: itoa Function in C : How to read all DestinationBuffer values (int) into String F DestinationBuffer values are decimal values. I am using this function in LWIP Echo server (Ethernetlite). Default Code ( itoa) char* itoa(int val, int base){ static char buf[32] = {0}; int i = 30...
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    XilinX LWIP : Whether Ethernetlite design can be implemented without using AXI UART

    Thanks for your response. Did you mean AXI Traffic Generator (ATG) and AXI Ethernetlite ? I am using AXI UARTLITE for printing the data in console. I am sending the data to AXI Ethernetlite from Aurora IP. In my current design, i have implemented the below process using the AXI UARTLITE. 1...
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    XilinX LWIP : Whether Ethernetlite design can be implemented without using AXI UART

    I am using KC705 board. I have implemented the data transfer between the PC and board using the AXI-UARTLITE, microblaze, AXI-Timer and Interrupt controller. Now, the same design I need to run the Axi-Ethernetlite design with microblaze and without using AXI-UARTLITE. Is it possible to...
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    itoa Function in C: How to read all DestinationBuffer values (int) into String Forma

    itoa Function in C : How to read all DestinationBuffer values (int) into String Forma For hardware implementation, I am writing this function to read the data in Hercules. In Hercules, integer data can be read in string format. So, i have tried itoa conversion in XSDK. I am running counter...
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    Need help in Python SOCKET Coding : For Xilinx EthernetLite LWIP

    Hello, Now i am able to print the data in Hercules, instead i need to print the data in Python Shell. I don`t know anything about Python Socket eventhough i have tried but i am not able to do that. Please apologize me and help in Python coding part. Thank you in advance The below...
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    How to interface NIOS II with Wiznet 5300 using tri-state conduit bridge?

    Still, i didn`t get any reply from Experts. Please consider this thread and response to me. Thanks in Advance I want to perform a connection between Nios and Ethernet Module Wiznet W5300. As of now, Using On-chip FIFO Memory core, i am able to read the data in NIOS console. Now, i need to...
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    Counter Using Onchip FIFO Memory Core (SOPC) and NIOS

    Hello, I am trying to implement counter module using MM-FIFO and to read the data in NIOS. 1. Enabling the counter from [1-bit PIO out (SOPC)] 2. Compiled Verilog code (counter), and created as a Symbol file (counter) 3. Interconnected counter module and Qsys component 4...
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    Help in Verilog Code: Timing Diagram Showing wrong result

    The following code is not giving the correct results! Modified Code always @ (posedge clk) begin temp1 <= trig; end assign detect = trig & ~temp1; /// EDGE DETECT assign temp2=temp1&&clk; always@(posedge temp2) if(reset)...
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    Help in Verilog Code: Timing Diagram Showing wrong result

    Hello, Through Verilog Code 1. Generating Trigger signal (trig) for 500ns 2. Generating Counter data I need to collect the counter data only at Positive edge (at the rising edge alone) of Trigger signal (not at the entire Positive cycle of Trigger signal). How can be possible. I...
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    Help in Verilog Code: Timing Diagram Showing wrong result

    Please you through the NIOS console (Previous). Why same data is printing for some times in console?
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    Help in Verilog Code: Timing Diagram Showing wrong result

    >>please give your clock frequency 50 MHZ Verilog code is correct as of now. But i need some modification to be done like positive edge detector. I want to collect only data of Positive(neck) edge of trig signal and store into register. - - - Updated - - - Timing Diagram I need to collect...
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    Help in Verilog Code: Timing Diagram Showing wrong result

    Sorry, It is not "wrong" timing diagram. I need to store neck edge (Positive) data once. Please find the attachment. I have compiled that Code in Altera. Counter data like 0, 27,54, 81 is repeating for long time. I need to collect those data only once. Please tell me how it can be...
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    Help in Verilog Code: Timing Diagram Showing wrong result

    Hi, No Compilation error but logic of timing diagram is wrong. I am generating Trigger signal for 500ns, and every neck edge (either positive or negative) of Trigger i am trying to store the counter in Register. Can anyone verify me code. I have simulated verilog Code in Quartus but...
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