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Recent content by Abdo_Mgdy

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    [SOLVED] Preventing using a certain cell in cadence encounter

    I didn't find "set_dont_use" command in encounter. I need a command performs the same functionality - - - Updated - - - I've figured it out. The command is "setDontUse <cell_name> <true | false>" - - - Updated - - - I've figured it out. The command is "setDontUse <cell_name> <true | false>"
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    [SOLVED] Preventing using a certain cell in cadence encounter

    How to forbid a certain cell from being placed in cadence encounter?
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    Finding certain string in file using bash shell scriot

    The output shoud be as follows: [syntax=txt] 0.008406 0.000132 ... [\syntax] And, no the value does not always come in the same line
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    Finding certain string in file using bash shell scriot

    I need to develop bash shell script extracting capacitance values of nets from post pnr spf file and put them in a column vector. The spf file is like following: *|NET top33_dft_1/top33_orig_1/rf0_1/n503 0.008406PF *|I (top33_dft_1/top33_orig_1/rf0_1/U924:A1 *+...
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    Time Constraints in Placement

    You don't have to do this .. you read the sdc file at the floorplan stage if you readed the .v design, otherwise you can read the ddc file which includes the constraints info of the design.
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    DFT- Circuit Netlist

    I think you should use Synopsys Design Vision tool or any other equivalent one.
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    Different ways of reading design in ICC

    The difference is that if you follow the first way you will have to read the sdc file generated by DC, since if you imported the ddc file you won't have to do this; because ddc file has the constraints information of the design. I don't understand the second question; DC doesn't do floorplan!
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    SRAM1RW512x32 module for PULPino microprocessor

    I've cloned the rtl files of PULPino microprocessor from git-hub, I'm trying to synthesize it but I think there's a missing module named 'SRAM1RW512x32'. It was instantiated in "sp_ram_bank_2.sv" module. Can someone help, please?
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    [SOLVED] [moved] Routing signal like clock tree in Cadence Encounter

    It doesn't toggle like clock, this is right .. but it's highly loaded, it's supposed to reach every flop in the design , so it need to be buffered such like clock tree
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    [moved] Adding lockup latches manually in Cadence Encounter

    Manually you mean??
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    [SOLVED] [moved] Routing signal like clock tree in Cadence Encounter

    I need to route scan_en signal as clock tree network in Cadence Encounter, so that it reaches all scan flops with minimum skew.
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    [moved] Adding lockup latches manually in Cadence Encounter

    I'm working on Cadence Encounter and I need to add lockup latches in the scan chain, how can I do this in the PnR phase?
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