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Recent content by aasai

  1. A

    Cache in memory(MESI Protocol)

    Hi all, In multi processor system, if a cache in modified state then how and why the write miss happened . If write miss is happened means what is the next state. And how the shared write in shared state and if it happened means what is the next state .... Thanks &...
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    Difference between DIMM and SIMM in memory slots?

    Hi Thanks for your valuable response ...... actually DIMM means it is accessed by the two side and SIMM is one side access .. i am right ... what is that two side and one side access exactly ........... I thought, can do only one operation either read or write to that respective rank of...
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    Difference between DIMM and SIMM in memory slots?

    please anybody explain me elaborately the difference between DIMM and SIMM in memory slots ?? When i read the whole motherboard architecture of pc ? i come accross the DIMM in memory slots .... why DIMM replaces SIMM in memory slots and what is that advantages DIMM over SIMM ? Please...
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    Difference between SSD and SATA

    Hi Thanks for your valuable response ..........
  5. A

    ASIC vs SOC AND vs FPGA

    I think all Asic is not an SOC, .................. but all SOC is an ASIC .... Because Soc is an complete system designed by following the ASIC design flow... But simple ASIC contain only few functionality,.. so i think this simple ASIC doesn't contain that SOC properties .....
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    Difference between SSD and SATA

    Hi everyone, I want to know what is the technical difference between Solid State Drive(SSD) and SATA .................. Regards Aasai
  7. A

    Write and Read Operation in RAM(memory)

    Hi Everyone, I have one doubt in Dual port Ram ......... Now i am trying to do read and write operation exactly in same clock cycle in to the ram....... which one happen first whether read or write ..... If read means ... why ?? If write means ... why ...
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    Regarding Asynchronous FIFO

    Thank you very much for your reply sir, I agree with your concepts, But my case is different from the normal asynchronous fifo... In normal asy fifo If full is high write operation is halted... If empty is high read operation is halted.. But in our case 1. We...
  9. A

    Regarding Asynchronous FIFO

    Hi , In simple Asynchronous fifo , writing using clk1 & reading using clk2 , now i m trying to implement the Full & Empty Status flag for that i ==> Set the Direction Signal to High when Write_address( or Write_pointer ) is less than Read_address( or Read_pointer ) && i.e. ( Write_pointer >...
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