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Regarding Asynchronous FIFO

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aasai

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Hi ,

In simple Asynchronous fifo , writing using clk1 & reading using clk2 , now i m trying to implement the Full & Empty Status flag for that i
==> Set the Direction Signal to High when Write_address( or Write_pointer ) is less than Read_address( or Read_pointer ) &&
i.e. ( Write_pointer > Read_pointer ) then Direction = 1;

Reset the Direction Signal to Low when Write_address( or Write_pointer ) is greater than Read_address( or Read_pointer )
i.e. ( Write_pointer < Read_pointer ) then Direction = 0;

Case 1: ( Full Flag )
I assert status Full flag When Direction Signal is Set to High && ( Write_pointer == Read_pointer ).,
i.e. ( Direction == 1 && ( Write_pointer == Read_pointer ) ) then Full = 1;

if not i deassert status Full flag to Zero (Low).

Case 2: ( Empty Flag )
I assert status Empty flag When Direction Signal is Set to Low && ( Write_pointer == Read_pointer ).,
i.e. ( Direction == 0 && ( Write_pointer == Read_pointer ) ) then Empty = 1;

if not i deassert status Empty flag to Zero (Low).

Here I have Problem when Comparing Write_pointer && Read_pointer to assert Empty or Full
i.e. ( Write_pointer == Read_pointer )

because here the two Pointers are from Two differernt clk domains so i need to do double synchronization for anyone of the Pointer for synchronization with respect to the other clk domain .

During Comparision of Pointers now i can compare only Write_pointer with two clk delay Read_pointer because of Double synchronization of Read_pointer.
i.e. ( Write_pointer == two_clk_delay_Read_pointer )

if i compare like above equation means i am having the problem of missing the exact ( Write_pointer == Read_pointer ) condition ..........
but i want to compare the exact ( Write_pointer == Read_pointer ) .

So Plz givre me solutions regarding or if you are following any buffer mangement techniques kindly discuss.

thank you for your time.
 

lostinxlation

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During Comparision of Pointers now i can compare only Write_pointer with two clk delay Read_pointer because of Double synchronization of Read_pointer.
i.e. ( Write_pointer == two_clk_delay_Read_pointer )

if i compare like above equation means i am having the problem of missing the exact ( Write_pointer == Read_pointer ) condition ..........
but i want to compare the exact ( Write_pointer == Read_pointer ) .
.
You cannot detect rd_p==wr_p exactly at the time it happens due to the nature of asynchronicity. In fact, it is OK to use a delayed read pointer to generate FULL condition. Why ? Hint is advancing read pointer doesn't cause FULL condition, but advancing write pointer does.
The similar rule applies to EMPTY as well.
 
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aasai

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Thank you very much for your reply sir,

I agree with your concepts, But my case is different from the normal asynchronous fifo...

In normal asy fifo
If full is high write operation is halted...
If empty is high read operation is halted..

But in our case
1. We assume that, we need to assert underrun and overrun status, which means
that write and read operations are not halted even though any of the status are
asserted ...
i.e We are not protecting(halting) write and read operation flow like normal fifo

for example..
Let us assume w_pr = 4 and r_pr = 6 , 2_clk_delay_r_pr = 4
i.e (w_pr == 2_clk_delay_r_pr) then overrun is asserted

According to your clarification we are also asserting Overrun status
continuously when w_pr and r_pr are incrementing simultaneously with
2 location difference
i.e w_pr = 4,5,6,7,8 , r_pr = 6,7,8,9 and 2_clk_delay_r_pr = 4,5,6,7,8
overrun = 1,1,1,1 ... continuously....
Is it correct or any modification needed ? ...................

2. In this case how to assert underrun and overrun conditions .. is it different
from full and empty status flag ?

i am waiting for your reply sir ...................
Thank you for your time......
 

lostinxlation

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I think it's difficult to keep the real time overrun/underrun status if read clock and write clock are independent, since one clock domain doesn't know what other clock domain is doing until a certain time passes for synchronization.

According to your clarification we are also asserting Overrun status
continuously when w_pr and r_pr are incrementing simultaneously with
2 location difference
i.e w_pr = 4,5,6,7,8 , r_pr = 6,7,8,9 and 2_clk_delay_r_pr = 4,5,6,7,8
overrun = 1,1,1,1 ... continuously....
Is it correct or any modification needed ? ...................
It's not accurate and it may miss overrun/underrun status in a certain case, but I guess that's the best I can think of, if two clocks are totally asynchronous.
 

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