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Hi Fvm,
ya i was talking about the same thing. I got a code regarding the same.
module add3(in,out);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @ (in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <=...
Hi,
I am new to verilog coding. I have a problem in handling strings.
In my implementation I will receive a parameter value from DSP to my FPGA as 32'd58710000, I have to convert each digit to ASCII and send to another module.
like 5 = 35 in ascii
8 = 38 in ascii and so on.
My problem...
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