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Recent content by a.pareek

  1. A

    problem with SDF backannotation in scirocco

    I tried doing a smaller design like a counter and its giving me similar errors as in Baud rate generator. I am listing the errors here. I am attaching the sdf file and the structural vhdl file also the testbench for the counter. I am getting the following errors. The simulator fails to parse the...
  2. A

    problem with SDF backannotation in scirocco

    I was trying to implement a Baud Rate Generator which was originally designed in VHDL in encounter. So, I first synthesized it using Synopsys DC, created a structural Verilog netlist and generated a timing file(sdc) for using in encounter. I was able to place and route it in encounter and...
  3. A

    sroute error in SoC encounter

    Hey, try sroute before you place the cells in encounter. Thanks, Abhishek
  4. A

    Who has the SoC encounter Lab?

    encounter workshop soc you can try this link for a tutorial on encounter. It helped me a lot. http://www.chiptalk.org/modules/wfsection/article.php?articleid=1 Thanks Abhishek
  5. A

    problem with SDF backannotation in scirocco

    I am facing a problem with back-annotating the SDF file generated by encounter into scirocco for a post layout simulation. I read in the sdf file using DC and generated a new sdf but i am getting errors. Well, I can back-annotate the sdf files for combinational circuits but not for sequential...
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