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Hi everybody
I have some questions and need your help:
1- why body connection is important? (I know one of the reasons. see q.3)
2- I have designed a simple circuit at schematic level. I have connected the bodies of
all mosfets to correct voltage level. I use LayoutXL in cadence to create...
Re: About TSMC18rf
Thanks erikl
I have few more questions.
1- witch process should one use for KHz application?
2- Is there any matter if one uses rf process for KHz application? And does it need special configurations?
3- Are the processes different at final cost?
Thanks
Hi everybody
I am new to layout design. I need some sample layouts at TSMC 180nm.
sometimes I face simple questions that a good sample layout can help me.
Could anyone help me please.
Thanks
Hi everybody
What is the suitable metal layer for CLOCK signal in large digital design (Transistor numbers>1000000)? and why?
Could you please introduce me a good reference describing such subjects?
Thanks
Hi everybody
I have 2 questions:
1- How many metal layers is available at 180nm technology of TSMC?
2- Is there any restrictions on the number of metal layers to use?
Thanks
Re: How can change background color in virtuoso schematic ed
Thanks my GOD
I am very very happy that I could change the background color from Black to white!
:D :D :D :D :D :D :D :D :D :D :D :D :D :D :D :D :D :D :D :D :D :D :D :D
And I want to share this happiness with you by telling you...
Re: How can change background color in virtuoso schematic ed
Thanks for your replay rfsystem.
At Display Resource Editor, I found background drawing and changed its
Fill and Outline colors from 'black' to 'white' and saved it in a new .drf file, then I exited this window and
loaded this new...
Hi bigdogguru
No. this is not a rhetorical question.
Infact I want to choose one of the mentioned solutions by a strong statistical reason.
if for example at 60% of application the clock enable is connected to a fixed active voltage level then it is better
to choose the second solution because...
Hi everybody
I have trouble with the black background of Cadence tools (for example in virtuoso schematic editor) when I want to prepare my reports.
How do you deal with this problem?
thanks
Hi everybody
I have a statistical question about the application of clock enable signal. I want to know How many percent of applications connect the clock enable to a fixed active voltage level (and what are some of these applications?) and How many percent of applications connect the clock...
Hi everybody
I want to connect for example the Vdd terminals of all components together without using wire at virtuoso schematic editor.
In some other softwares we can use labels to do this. at cadence I can use Pins to do this but I am afraid that get into trouble at next steps of my design...
By thanks to those send above replies , none of them could help me :cry:
I use IC5 and you can detect my problem at attached picture.
Do you know any other useful methods?
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